1. Field of the Invention
The present invention relates to the field of integrated circuits having scan chains for testing the integrated circuits; more specifically, it relates to method for selecting a set of patterns for diagnostic testing of the scan chains themselves.
2. Background of the Invention
Scan chains are used in integrated circuits to facilitate test. Like the circuits they are designed to test, scan chains are also susceptible to design errors and process defects. Because of this, the first tests applied to an integrated circuit chip are those tests specifically created to test the functionality of the scan chains. Often it is the case that the testing of scan chains finds more faults than the combinational logic testing that follows. While scan chain tests are able to detect failing scan chains, diagnostics based on current scan chain patterns fail to find the point of failure within the scan chains and thus an important component of yield learning is lost. Therefore, there is a need for an improved scan diagnostic pattern set.